qhdl Package

qhdl Package

qhdl Module

This module contains the code to convert a circuit specified in QHDL into a Gough-James circuit expression.

The other module in this package qhdl_parser implements an actual parser for the qhdl source text, while this file then converts structured netlist information into a circuit expression.

For more details on the QHDL syntax, see The QHDL Syntax.

class qnet.qhdl.qhdl.Architecture(identifier, entity, components, signals, assignments, global_assignments={})[source]

Bases: qnet.qhdl.qhdl.QHDLObject

global_in = {}
global_inout = {}
global_out = {}
in_to_signal = {}
inout_to_signal = {}
lossy_signals = []
out_to_signal = {}
signal_to_global_in = {}
signal_to_global_out = {}
signals = []
to_circuit(identifier_postfix='')[source]

Compute a circuit algebra expression from the QHDL code and return the circuit expression, the all_symbols appearing in it and the component instance assignments

to_qhdl(tab_level=0)[source]
class qnet.qhdl.qhdl.BasicInterface(identifier, generics, ports)[source]

Bases: qnet.qhdl.qhdl.QHDLObject

cid = 0
generic_identifiers

The generic_identifiers property.

generics_to_qhdl(tab_level)[source]
gids

The generic_identifiers property.

in_port_identifiers = []
inout_port_identifiers = []
out_port_identifiers = []
port_identifiers

The port_identifiers property.

ports_to_qhdl(tab_level)[source]
to_qhdl(tab_level)[source]
class qnet.qhdl.qhdl.Component(identifier, generics, ports)[source]

Bases: qnet.qhdl.qhdl.BasicInterface

to_qhdl(tab_level=0)[source]
class qnet.qhdl.qhdl.Entity(identifier, generics, ports)[source]

Bases: qnet.qhdl.qhdl.BasicInterface

to_qhdl(tab_level=0)[source]
exception qnet.qhdl.qhdl.QHDLError[source]

Bases: Exception

class qnet.qhdl.qhdl.QHDLObject[source]

Bases: object

to_python()[source]
to_qhdl()[source]
qnet.qhdl.qhdl.dict_keys_sorted_by_val(dd)[source]
qnet.qhdl.qhdl.gtype_compatible(c_t, g_t)[source]
qnet.qhdl.qhdl.my_debug(msg)[source]

qhdl_parser Module

The PLY-based QHDLParser class.

class qnet.qhdl.qhdl_parser.QHDLParser(**kw)[source]

Bases: qnet.misc.parser.Parser

create_circuit_lib(arch_id=None)[source]
p_architecture_declaration(p)[source]

architecture_declaration : ARCHITECTURE ID OF ID IS architecture_head BEGIN instance_mapping_assignment_list feedleft_assignment_list END opt_arch opt_id SEMI

p_architecture_head(p)[source]

architecture_head : component_declaration_list signal_list

p_complex(p)[source]

complex : LPAREN simple_number COMMA simple_number RPAREN

p_component_declaration(p)[source]

component_declaration : COMPONENT ID generic_clause port_clause END COMPONENT opt_id SEMI

p_component_declaration_list(p)[source]
component_declaration_list : component_declaration_list component_declaration
component_declaration
p_empty(p)[source]

empty :

p_entity_declaration(p)[source]

entity_declaration : ENTITY ID IS generic_clause port_clause END opt_entity opt_id SEMI

p_error(p)[source]
p_feedleft_assignment(p)[source]
feedleft_assignment : ID FEEDLEFT ID SEMI
empty
p_feedleft_assignment_list(p)[source]
feedleft_assignment_list : feedleft_assignment_list feedleft_assignment
feedleft_assignment
p_feedright_generic_assignment(p)[source]
feedright_generic_assignment : ID FEEDRIGHT id_or_value
id_or_value
p_feedright_generic_assignment_list(p)[source]
feedright_generic_assignment_list : feedright_generic_assignment_list COMMA feedright_generic_assignment
feedright_generic_assignment
p_feedright_port_assignment(p)[source]
feedright_port_assignment : ID FEEDRIGHT ID
ID
p_feedright_port_assignment_list(p)[source]
feedright_port_assignment_list : feedright_port_assignment_list COMMA feedright_port_assignment
feedright_port_assignment
p_generic_clause(p)[source]
generic_clause : generic_statement
empty
p_generic_default(p)[source]
generic_default : ASSIGN number
empty
p_generic_entry_group(p)[source]

generic_entry_group : id_list COLON generic_type generic_default

p_generic_list(p)[source]
generic_list : generic_list SEMI generic_entry_group
generic_entry_group
p_generic_map(p)[source]
generic_map : GENERIC MAP LPAREN feedright_generic_assignment_list RPAREN SEMI
empty
p_generic_statement(p)[source]

generic_statement : GENERIC LPAREN generic_list opt_semi RPAREN SEMI

p_generic_type(p)[source]

generic_type : REAL | COMPLEX | INT

p_id_list(p)[source]
id_list : id_list COMMA ID
ID
p_id_or_value(p)[source]
id_or_value : ID
number
p_instance_mapping_assignment(p)[source]

instance_mapping_assignment : ID COLON ID generic_map port_map

p_instance_mapping_assignment_list(p)[source]
instance_mapping_assignment_list : instance_mapping_assignment_list instance_mapping_assignment
instance_mapping_assignment
p_int(p)[source]

int : ICONST

p_io_port_entry_group(p)[source]

io_port_entry_group : id_list COLON INOUT signal_type

p_non_io_port_entry_group(p)[source]

non_io_port_entry_group : id_list COLON signal_direction signal_type

p_non_io_port_list(p)[source]
non_io_port_list : non_io_port_entry_group SEMI non_io_port_list
non_io_port_entry_group
p_number(p)[source]
number : simple_number
complex
p_opt_arch(p)[source]
opt_arch : ARCHITECTURE
empty
p_opt_entity(p)[source]
opt_entity : ENTITY
empty
p_opt_id(p)[source]
opt_id : ID
empty
p_opt_semi(p)[source]
opt_semi : SEMI
empty
p_port_clause(p)[source]
port_clause : port_statement
empty
p_port_list(p)[source]
port_list : with_io_port_list
non_io_port_list
p_port_map(p)[source]
port_map : PORT MAP LPAREN feedright_port_assignment_list RPAREN SEMI
empty
p_port_statement(p)[source]

port_statement : PORT LPAREN port_list opt_semi RPAREN SEMI

p_real(p)[source]

real : FCONST

p_signal_direction(p)[source]
signal_direction : IN
OUT
p_signal_entry_group(p)[source]

signal_entry_group : SIGNAL id_list COLON signal_type SEMI

p_signal_list(p)[source]
signal_list : signal_list signal_entry_group
signal_entry_group
p_signal_type(p)[source]
signal_type : FIELDMODE
LOSSY_FIELDMODE
p_simple_number(p)[source]
simple_number : int
real
p_top_level_list(p)[source]
top_level_list : top_level_list top_level_unit
top_level_unit
p_top_level_unit(p)[source]
top_level_unit : entity_declaration
architecture_declaration
p_with_io_port_list(p)[source]
with_io_port_list : io_port_entry_group SEMI non_io_port_list
io_port_entry_group
parse(inputstring)[source]
reserved = {'architecture': 'ARCHITECTURE', 'begin': 'BEGIN', 'complex': 'COMPLEX', 'component': 'COMPONENT', 'end': 'END', 'entity': 'ENTITY', 'fieldmode': 'FIELDMODE', 'generic': 'GENERIC', 'in': 'IN', 'inout': 'INOUT', 'int': 'INT', 'is': 'IS', 'lossy_fieldmode': 'LOSSY_FIELDMODE', 'map': 'MAP', 'of': 'OF', 'out': 'OUT', 'port': 'PORT', 'real': 'REAL', 'signal': 'SIGNAL'}
start = 'top_level_list'
t_ASSIGN = ':='
t_COLON = ':'
t_COMMA = ','
t_FCONST = '-?((\\d+)(\\.\\d+)(e(\\+|-)?(\\d+))? | (\\d+)e(\\+|-)?(\\d+))'
t_FEEDLEFT = '<='
t_FEEDRIGHT = '=>'
t_ICONST = '-?\\d+'
t_ID(t)[source]

[_A-Za-z][w_]*

t_LPAREN = '\\('
t_NEWLINE(t)[source]

n+

t_RPAREN = '\\)'
t_SEMI = ';'
t_comment(t)[source]

–[^n]*

t_error(t)[source]
t_ignore = ' \t\x0c'
tokens = ['MAP', 'GENERIC', 'COMPONENT', 'PORT', 'IN', 'ENTITY', 'SIGNAL', 'OUT', 'COMPLEX', 'REAL', 'END', 'BEGIN', 'IS', 'OF', 'INOUT', 'LOSSY_FIELDMODE', 'INT', 'ARCHITECTURE', 'FIELDMODE', 'ID', 'ICONST', 'FCONST', 'ASSIGN', 'FEEDRIGHT', 'FEEDLEFT', 'LPAREN', 'RPAREN', 'COMMA', 'SEMI', 'COLON']